reset vector → 0x00000000 · booting profile
Mapping the stack from silicon to software.
Computer Science student working at the intersection of systems engineering, software architecture, and systems AI — building optimized applications while engineering hardware structures from the register file up.
.about — segment base
Kareem Taiye
Computer Science student currently building a RISC-V processor from the ground up — hand-encoding RV32I instruction formats, designing a register file and RAM in SystemVerilog, and tracing programs through the full compile → assemble → link → load pipeline down to raw memory addresses.
The throughline across my work is simple: understand a system well enough to build it, not just use it. That applies as much to a distributed backend as it does to a datapath — I care about what's actually happening underneath the abstraction.
Currently working toward research experience in computer architecture and systems, building on Harris & Harris and Patterson & Hennessy, with bare-metal programming and OS fundamentals next on the path.
.systems — architecture & hardware
Systems & Architecture
RISC-V from the Ground Up
An in-progress build of a RISC-V processor, following Harris & Harris — SystemVerilog modules for a dual-read/single-write register file and synchronous-write/async-read RAM, verified against hand-encoded machine code and real toolchain output (GCC + objdump). Documented as a running set of insight-pattern notes: instruction formats, opcode bit structure, addressing modes, linker relaxation, exceptions and CSRs.
.software — engineering projects
Software Engineering
Research Paper Management System
A distributed backend system with async task queues, real-time WebSocket notifications, full-text search, and an Nginx gateway with observability built in.
Project — coming soon
Reserved slot. Details to follow.
Project — coming soon
Reserved slot. Details to follow.
.research — interests & direction
Research & Systems AI
Working toward research assistant experience in computer architecture and systems — the layer where hardware constraints and software design meet. Building the foundation deliberately: complete a working RISC-V core, then extend into memory hierarchy, pipelining, and OS fundamentals before reaching out to research groups.
Harris & Harris (RISC-V, digital logic) → Patterson & Hennessy (pipelining, memory hierarchy, quantitative architecture).
Computer architecture, memory systems, and the systems side of applied ML — efficient infrastructure, hardware acceleration, systems for AI.
Complete a working single-cycle RISC-V processor in SystemVerilog, then move into bare-metal programming before OS-level work.
.resume — object file
Resume
Kareem Taiye — Resume
One page. Systems & software engineering, RISC-V / hardware work, and education. Updated —.
.stack — get in touch
Contact
Open to conversations about systems research, RISC-V, or opportunities where hardware and software design meet.